# ans1.py -R -full64 -sverilog \
#   -timescale=1ns/1ps \
#   -y rtl \
#   -f rtl.flist \
#   +warn=none \
#   +vpdfile+debug.vpd

import sys

my_args = {}
my_args_plus = {}
def args_parse(args):
    global my_args
    global my_args_plus
    k = ""
    v = ""

    args = args[1:]
    while len(args) > 0:
        arg = args.pop()
        if not arg.startswith('-') and not arg.startswith('+'):
            arg2 = args.pop()
            k = arg2[1:]
            if arg2.startswith('-'):
                my_args[k] = arg
            elif arg2.startswith('+'):
                my_args_plus[k] = arg
                
        elif arg.startswith('-'):
            arg = arg[1:]
            if arg.find('=') != -1:
                lst = arg.split('=')
                k = lst[0]
                my_args[k] = lst[1]
            else:
                my_args[arg] = "true"

        elif arg.startswith('+'):
            arg = arg[1:]
            if arg.find('=') != -1:
                lst = arg.split('=')
                k = lst[0]
                my_args_plus[k] = lst[1]
            elif arg.find('+') != -1:
                lst = arg.split('+')
                k = lst[0]
                my_args_plus[k] = lst[1]
            else:
                my_args_plus[arg] = "true"

args_parse(sys.argv)
print(my_args)
print(my_args_plus)
if 'sverilog' in my_args:
    print('exists sverilog option')
if 'vpdfile' in my_args_plus:
    print('vpd file name: ', my_args_plus['vpdfile'])